This invention relates to the transfer of data within a data processing system, and more specifically to the interchange of data among the data units of one or more data processing systems. It provides the capability of maintaining a number of different data transfer streams between two or more data units, simultaneously, by use of time division multiplexing.
Most data processing systems include a data bus to which system data units, such as processors, peripheral interfaces, and memory devices, are coupled in parallel. The bus provides a common conduction path on which the units transfer data between themselves. In order to transfer data to another unit, a unit gains access to the bus for a period of time sufficient to complete the transfer.
Older data systems normally comprise a bus linking a system processor, system memory, and one or more peripheral data units such as data keyboards and off-line data storage devices. In these systems the processor conventionally includes a bus access controller which autocratically grants access to the bus according to the requirements of the processor. Characteristically all of the data transfers on the bus are initiated and controlled by the processor through the controller.
In such systems control of communications between data units by the system processor typically limits the efficiency of communications between the data units. While this problem has been overcome in some large scale computing systems by crossbar logic circuitry, such architecture is inordinately complex and, hence, impractical for many applications.
More recent data processing systems are marked by the distribution of processing capability and responsibility among a plurality of separate, autonomous processors. As a consequence the requirements for bus access are no longer centralized and a number of processors may raise concurrent, equally urgent requests for use of the bus.
Consequently a means and a mode for bus access control is required which satisfactorily resolves competing bus access requests from a plurality of data processing system units. Such satisfactory resolution should provide each processing system unit with timely access in order to preserve the freshness of the data which it seeks to transfer to or obtain from another unit. At the same time the bus system control mechanization should not produce an unreasonable decrease in system operating efficiency by adding unnecessarily to the amount of system operational time which is devoted solely to implementing the control.
A data processing system exemplifying the older technique of data bus control is disclosed, for example, in Cohen et al., U.S. Pat. No. 3,710,324, wherein a controller responds to requests by system units for data bus access by granting control of the data bus operation to the requesting units on a basis of preestablished priority. When control is granted to a data unit, all other bus users are excluded from access to the bus while the unit receiving the grant conducts a data transfer on the bus. Several features of the bus control mechanization of this system reduce its operational efficiency. For example, in establishing control, a plurality of successive handshaking signals precede the actual data transfer for which control is obtained. Furthermore, a data transfer can comprise any one of a number of possible modes of operation, each of which require a separate synchronization procedure together with the means to implement it. Finally, there is only one path upon which system data may be interchanged. This means that the system memory response bandwidth is limited by the need to utilize the data bus for nonmemory data transfers as well as for memory access transfers.
Another type of data transfer system is taught in Durvasula et al., U.S. Pat. No. 4,245,303 wherein a memory element attached to a data transfer bus has associated with it a controller which prevents other units from addressing the memory when it is oversubscribed with data transfer requests. However, since the memories of this system are connected to a single data signal path in common with the other system elements, memory transfers must still compete with data transfers between other system elements. This competition unavoidably lengthens the aggregate memory response time of the system.
While many existing data transfer systems do exhibit a number of inefficiencies which use of a novel data transfer system may eliminate, it is neither practical nor possible to supplant all of the older systems with the new one. Rather a period of transition must follow the introduction of the new transfer system, during which the new system is applied to satisfy the transfer requirements of emerging data systems, while preexisting data systems continue to utilize the prior, inefficient transfer systems.
During the transition period, it would be desirable to operate an existing data transfer system in a coupled arrangement with a new system which would allow the systems to conduct inter-system data transfers. Such an arrangement could permit the existing system to enjoy the efficiency of the new system with a minimum of changes to existing software. Provision of an inter-system coupling device which could connect the systems in an efficient, complementary manner would constitute a desirable advancement of the data transfer art.